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MAX2055EUP Rev. A
RELIABILITY REPORT FOR MAX2055EUP PLASTIC ENCAPSULATED DEVICES
April 2, 2004
MAXIM INTEGRATED PRODUCTS 120 SAN GABRIEL DR. SUNNYVALE, CA 94086
Written by
Reviewed by
Jim Pedicord Quality Assurance Reliability Lab Manager
Bryan J. Preeshl Quality Assurance Executive Director
Conclusion The MAX2055 successfully meets the quality and reliability standards required of all Maxim products. In addition, Maxim's continuous reliability monitoring program ensures that all outgoing product will continue to meet Maxim's quality and reliability standards. Table of Contents I. ........Device Description II. ........Manufacturing Information III. .......Packaging Information IV. .......Die Information I. Device Description A. General The MAX2055 high-performance, digitally controlled, variable-gain, differential analog-to-digital converter (ADC) driver/amplifier (DVGA) is designed for use from 30MHz to 300MHz in base-station receivers. The device integrates a digitally controlled attenuator and a high-linearity single-ended-to-differential output amplifier, which can either eliminate an external transformer, or can improve the even-order distortion performance of a transformer-coupled circuit, thus relaxing the requirements of the anti-alias filter preceding an ADC. Targeted for ADC driver applications to adjust gain either dynamically or as a one-time channel gain setting, the MAX2055 is ideal for applications requiring high performance. The attenuator provides 23dB of attenuation range with 0.2dB accuracy. The MAX2055 is available in a thermally enhanced 20-pin TSSOP-EP package and operates over the -40C to +85C temperature range. V. ........Quality Assurance Information VI. .......Reliability Evaluation ......Attachments
B. Absolute Maximum Ratings Item All Pins to GND Input Signal (RF_IN) Output Power (RF_OUT) Operating Temperature Range Junction Temperature Storage Temperature Range Lead Temperature (soldering, 10s) Continuous Power Dissipation (TA = +85C) 28-Pin TSSOP Derates above +85C 28-Pin TSSOP Rating -0.3V to +(VCC + 0.25V) 20dBm 24dBm -40C to +85C +150C -65C to +165C +300C 2100mW 21.7mW/C
II. Manufacturing Information A. Description/Function: B. Process: C. Number of Device Transistors: D. Fabrication Location: E. Assembly Location: F. Date of Initial Production: Digitally Controlled, Variable-Gain, Differential ADC Driver/Amplifier GST4 325 Oregon, USA Philippines or Malaysia April, 2003
III. Packaging Information A. Package Type: B. Lead Frame: C. Lead Finish: D. Die Attach: E. Bondwire: F. Mold Material: G. Assembly Diagram: H. Flammability Rating: I. Classification of Moisture Sensitivity per JEDEC standard J-STD-020-A: 28-Pin TSSOP Copper Solder Plate Silver-filled epoxy Gold (1.2 mil dia.) Epoxy with silica filler Buildsheet # 05-9000-0419 Class: UL94-V0
Level 1
IV. Die Information A. Dimensions: B. Passivation: C. Interconnect: D. Backside Metallization: E. Minimum Metal Width: F. Minimum Metal Spacing: G. Bondpad Dimensions: H. Isolation Dielectric: I. Die Separation Method: 125 x 79 mils Si3N4 (Silicon nitride) Au None Metal1: 1.2; Metal2: 1.2; Metal3: 1.2; Metal4: 5.6 microns (as drawn) Metal1: 1.6; Metal2: 1.6; Metal3: 1.6; Metal4: 4.2 microns (as drawn) 5 mil. Sq. SiO2 Wafer Saw
V. Quality Assurance Information A. Quality Assurance Contacts: Jim Pedicord (Manager, Reliability Operations) Bryan Preeshl (Executive Director of QA) Kenneth Huening (Vice President) B. Outgoing Inspection Level: 0.1% for all electrical parameters guaranteed by the Datasheet. 0.1% For all Visual Defects.
C. Observed Outgoing Defect Rate: < 50 ppm D. Sampling Plan: Mil-Std-105D VI. Reliability Evaluation A. Accelerated Life Test The results of the 150C biased (static) life test are shown in Table 1. Using these results, the Failure Rate () is calculated as follows: = 1 = MTTF 1.83 (Chi square value for MTTF upper limit) 192 x 9823 x 45 x 2 Temperature Acceleration factor assuming an activation energy of 0.8eV = 10.78 x 10-8 = 10.78 F.I.T. (60% confidence level @ 25C)
This low failure rate represents data collected from Maxim's reliability qualification and monitor programs. Maxim also performs weekly Burn-In on samples from production to assure reliability of its processes. The reliability required for lots which receive a burn-in qualification is 59 F.I.T. at a 60% confidence level, which equates to 3 failures in an 80 piece sample. Maxim performs failure analysis on rejects from lots exceeding this level. The Burn-In Schematic (Spec.# 06-7097) shows the static circuit used for this test. Maxim also performs 1000 hour life test monitors quarterly for each process. This data is published in the Product Reliability Reports (RR-1M & RR-B3A). B. Moisture Resistance Tests Maxim evaluates pressure pot stress from every assembly process during qualification of each new design. Pressure Pot testing must pass a 20% LTPD for acceptance. Additionally, industry standard 85C/85%RH or HAST tests are performed quarterly per device/package family. C. E.S.D. and Latch-Up Testing The CR17 die type has been found to have all pins able to withstand a transient pulse of +/-200V, per Mil-Std883 Method 3015 (reference attached ESD Test Circuit). Latch-Up testing has shown that this device withstands a current of 250mA.
Table 1 Reliability Evaluation Test Results MAX2055EUP
TEST ITEM TEST CONDITION FAILURE IDENTIFICATION SAMPLE SIZE NUMBER OF FAILURES
Static Life Test (Note 1) Ta = 150C Biased Time = 192 hrs. Moisture Testing (Note 2) Pressure Pot Ta = 121C P = 15 psi. RH= 100% Time = 168hrs. Ta = 85C RH = 85% Biased Time = 1000hrs.
DC Parameters & functionality
45
0
DC Parameters & functionality
77
0
85/85
DC Parameters & functionality
77
0
Mechanical Stress (Note 2) Temperature Cycle -65C/150C 1000 Cycles Method 1010 DC Parameters & functionality 77 0
Note 1: Life Test Data may represent plastic DIP qualification lots. Note 2: Generic process/package data.
Attachment #1 TABLE II. Pin combination to be tested. 1/ 2/
Terminal A (Each pin individually connected to terminal A with the other floating) 1. 2. All pins except VPS1 3/ All input and output pins
Terminal B (The common combination of all like-named pins connected to terminal B) All VPS1 pins All other input-output pins
1/ Table II is restated in narrative form in 3.4 below. 2/ No connects are not to be tested. 3/ Repeat pin combination I for each named Power supply and for ground (e.g., where VPS1 is VDD, VCC, VSS, VBB, GND, +VS, -VS, VREF, etc). 3.4 a. b. Pin combinations to be tested. Each pin individually connected to terminal A with respect to the device ground pin(s) connected to terminal B. All pins except the one being tested and the ground pin(s) shall be open. Each pin individually connected to terminal A with respect to each different set of a combination of all named power supply pins (e.g., VSS1, or VSS2 or VSS3 or VCC1 , or VCC2 ) connected to terminal B. All pins except the one being tested and the power supply pin or set of pins shall be open. Each input and each output individually connected to terminal A with respect to a combination of all the other input and output pins connected to terminal B. All pins except the input or output pin being tested and the combination of all the other input and output pins shall be open.
c.
TERMINAL C
R1 S1 R2
TERMINAL A REGULATED HIGH VOLTAGE SUPPLY
S2 C1
DUT SOCKET
SHORT CURRENT PROBE (NOTE 6)
TERMINAL B
R = 1.5k C = 100pf
Mil Std 883D Method 3015.7 Notice 8
TERMINAL D
DOCUMENT I.D. 06-7097
REVISION B B
MAXIM
TITLE: BI
Circuit (MAX2055) CR17Z
PAGE
2

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